====== Semiconductor models ======

===== Mixed-mode Logic gates =====

==== Native models ====

  * [[http://gnucap.org/gnucap-man-html/gnucap-man080.html|logic]]


=== Syntax ===

== Verilog mode ==

Device:
  gatetype #(.model(process)) Uxxxxx (out, in1, in2, ...);
Paramset:
  paramset mname logic;\
  {args}\
  endparamset

== Spice mode ==

Device:
  Uxxxxxxx out in1 in2 ... process gatetype
Model (required):
  .model mname LOGIC {args}
Subcircuit definition (optional):
  .subckt subname nodes
  subcircuit description
  .ends