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gnucap:manual:examples:verilog_basics [2023/04/18 05:38]
felixs created
gnucap:manual:examples:verilog_basics [2023/04/19 07:47] (current)
felixs voltage probes
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 device instances at top level. But we do (under restrictions). This way device instances at top level. But we do (under restrictions). This way
 the top level can act as a test bench, as needed. the top level can act as a test bench, as needed.
 +
 +=== node voltages inside a module instance ===
 +
 +Nodes in a subcircuit instance are not mapped, and can't be probed directly through "print".
 +Instead, either use a "meter", or probe the voltage at the port of a known device.
 +
 +<code>
 +gnucap> verilog
 +verilog> module divid();
 +verilog>  resistor #(.r(11)) R1(in, out);
 +verilog>  resistor #(.r(22)) R2(out, 0);
 +verilog>  vsource #(.dc(1.23)) V1(in, 0);
 +verilog>  meter mout(out, 0, 0, 0);
 +verilog> endmodule
 +
 +verilog> divid #() mydiv();
 +
 +verilog> print dc v(mydiv.mout) v1(mydiv.R1)
 +verilog> dc
 +</code>
 +
 +You could as well maintain connectivity to the top level, which has named ports. Note how the top level is not instanciated, and the nodes are accessible by name.
 +
 +<code>
 +gnucap> verilog
 +verilog> module divid(out);
 +verilog>  resistor #(.r(11)) R1(in, out);
 +verilog>  resistor #(.r(22)) R2(out, 0);
 +verilog>  vsource #(.dc(1.23)) V1(in, 0);
 +verilog>  meter mout(out, 0, 0, 0);
 +verilog> endmodule
 +
 +verilog> divid #() mydiv(out);
 +
 +verilog> print dc v(out)
 +verilog> dc
 +</code>
gnucap/manual/examples/verilog_basics.txt · Last modified: 2023/04/19 07:47 by felixs
 
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