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gnucap:manual:languages:spice [2018/05/22 06:58] felixs created |
gnucap:manual:languages:spice [2026/02/16 04:36] (current) felixs spice update and reference verilog |
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| - | SPICE has irregular and confusing syntax. The preferred way to use SPICE models is through subckt declarations. A subckt declaration can be parsed while the language is set to spice. Case sensitivity can be enabled (default is off in spice), in order to avoid problems later, when the netlist is expanded. | + | SPICE has irregular and confusing syntax. The preferred way to use SPICE netlists is through subckt declarations. A subckt declaration creates a type that can be used in any language. Case sensitivity can be enabled (default is off in Spice), in order to avoid problems later, when the netlist is expanded. |
| spice | spice | ||
| .options noinsensitive | .options noinsensitive | ||
| .subcircuit mydev(a, b) | .subcircuit mydev(a, b) | ||
| - | .parameter r=1 | + | .parameter r=1 |
| - | R1 a b r | + | R1 a b r |
| .ends | .ends | ||
| - | The device above may contain more elaborate models and/or behavioural modeling quirks. Regardless it is now available, e.g. after switching to verilog (verilog is case sensitive by default). | + | The device above may contain more elaborate models and/or behavioural modeling quirks. An instanciation in Spice will look like |
| + | |||
| + | X1 p 0 mydev r=1k | ||
| + | |||
| + | The instanciation in Verilog is possible as follows. Note that verilog is case sensitive. | ||
| verilog | verilog | ||
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| print dc v(p) i(my_resistor.R1) | print dc v(p) i(my_resistor.R1) | ||
| dc | dc | ||
| + | |||
| + | It is generally not required to use Spice netlists or models in Gnucap. When making the transition from Spice, [[gnucap:manual:tech:spice2verilog]] may be useful. | ||