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gnucap:manual:tech:modelgen [2023/05/04 11:05] felixs add introduction and ddt,idt |
gnucap:manual:tech:modelgen [2023/05/05 03:57] (current) felixs illustrate ddt |
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| remain possible, and will be considered later on. The ''idt'' operator is a simple | remain possible, and will be considered later on. The ''idt'' operator is a simple | ||
| adaptation of the ''ddt'' operator. | adaptation of the ''ddt'' operator. | ||
| + | |||
| + | To illustrate the implementation of a ddt filter, consider the contribution | ||
| + | statement ''I(p,n) <+ f2(ddt(f1(V(p,n)))''. It splits into | ||
| + | a voltage probe, a filter and a controlled source as follows | ||
| + | <code> | ||
| + | real t0; | ||
| + | t0 = V(p,n); | ||
| + | t0 = f1(t0); | ||
| + | t0 = ddt(t0); // (*) | ||
| + | t0 = f2(0); | ||
| + | I(p,n) <+ t0; | ||
| + | </code> | ||
| + | |||
| + | and happens to model a capacitor, if ''f1(x)==f2(x)==x''. All we need for the general case is ''ddt(t0)''. | ||
| + | The following subcircuit model implements a capacitor corresponding to the simplified contribution statement. | ||
| + | |||
| + | <code> | ||
| + | module cap(a, b) | ||
| + | parameter c | ||
| + | tcap #(c) store(i 0 a b); | ||
| + | resistor #(.r(1)) shunt(0 i); | ||
| + | vccs #(.gm(1)) branch_i(b a i 0); | ||
| + | endmodule | ||
| + | </code> | ||
| + | |||
| + | It contains a trans-capacitance device named "store". This device outputs a | ||
| + | current proportional to the time derivative of the voltage across ''(a,b)''. In | ||
| + | combination with the shunt resistor and the internal node ''i'' it represents a | ||
| + | ''ddt'' filter as required in (*), where the rhs implicitly acts as a voltage probe ''V(i)''. | ||
| + | |||
| + | In terms of implementation, the ''tcap'' device is a version of the Modelgen | ||
| + | ''fpoly_cap'' limited to 4 external nodes and without self-capacitance. | ||
| + | The ''va_ddt'' filter in Modelgen-Verilog retains the arbitrary number of nodes and adds the shunt resistance. | ||