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gnucap:user:language_plugin_for_qucs [2018/06/20 06:14]
felixs more on gnucsator
gnucap:user:language_plugin_for_qucs [2018/07/07 17:36] (current)
felixs some additions and rewording
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 The use is quite limited due to the interface between qucs and qucsator, but it defines a sort of interface between the projects. The use is quite limited due to the interface between qucs and qucsator, but it defines a sort of interface between the projects.
  
-gnucsator aims to be a drop-in replacement for gnucsator, that means it will +gnucsator aims to be a drop-in replacement for qucsator, that means it will 
-provide the components implemented in qucsator, +provide the components implemented in qucsator, 
-have to read the netlist (unless/until somebody fixes this) +have to read the netlist (unless/until somebody fixes this) 
-produce output equivalent to qucsator output ("dat" file format)+* interpret simulation commands (embedded into the netlist) like qucsator. 
-- interpret simulation commands (embedded into the netlist) like qucsator.+produce output equivalent to qucsator output ("dat" file format).
  
 == Example of a qucsator netlist file == == Example of a qucsator netlist file ==
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 First line shows the version of the qucs and the file path First line shows the version of the qucs and the file path
 +
 +_net gives information about in between which nodes the component is connected
  
 The list of the components in Qucs can be seen in the link below The list of the components in Qucs can be seen in the link below
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 TODO. tl;dr; some upside-down xml inspired layout without simulation labels. TODO. tl;dr; some upside-down xml inspired layout without simulation labels.
 +
  
 == description of the simulation commands == == description of the simulation commands ==
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 == Description of a schematic file == == Description of a schematic file ==
  
-The schematic format used in qucs is not worth the trouble. It will be easy to represent the schematic as a verilog netlist, once qucs supports additional file formats. (then drop the qucsator netlists).+The schematic format used in qucs is not currently used for simulation purposes. Qucs compiles an intermediate self-contained circuit representation ("netlist") including simulation commands before invoking qucsator. Hence the format used for the schematics (some XML-like format) is not relevant yet. It will be easy to represent the schematic as a standardized (e.g. verilognetlist, once Qucs supports additional file formats. This will make the schematic files more useful and the intermediate netlists obsolete.
  
 == Implementing the Components == == Implementing the Components ==
  
-We need to provide (most/all) of the components supported by qucsator. It would be possible to wrap them, using a wrapper similar to spice_wrapper (e.g. http://git.savannah.gnu.org/cgit/gnucap/gnucap-plugins.git/tree/qucs_wrapper.cc?h=qucs). It does not seem to be worth the troubleThe approach here +Qucs essentially provides a hardcoded set of components plus variants (paramsets) through a "component library". We need to provide (most/all) of the components supported by qucsator. It would be possible to wrap them, on an implementation/binary level using a wrapper similar to spice_wrapper (e.g. http://git.savannah.gnu.org/cgit/gnucap/gnucap-plugins.git/tree/qucs_wrapper.cc?h=qucs). This involves some effort and workarounds with no clear benefitIn particular, there are only few components, this could be used for.
-https://git.savannah.gnu.org/cgit/gnucap/gnucap-plugins.git/tree/STATUS?h=qucs aims at implementing the components in terms of modules that (re-)use existing gnucap components. Some components are written in Verilog-Aideally all would be implemented like this.+
  
-== misc +The approach here 
- +https://git.savannah.gnu.org/cgit/gnucap/gnucap-plugins.git/tree/STATUS?h=qucs aims at implementing the components in terms of modules that (re-)use some functionality of existing gnucap components. Some components can be directly wrapped through a subcircuit declaration or paramset. Others can be easily represented by subcircuits containing few components (a.k.a. macros). Ideally all components would be implemented in verilog-A. At the current stage it would make more sense to support user provided Verilog-A models in qucs. Some work has been done in that direction, but qucsator will not support Verilog-A input in the foreseeable future.
-_net gives information about in between which nodes the component is connected+
gnucap/user/language_plugin_for_qucs.txt · Last modified: 2018/07/07 17:36 by felixs
 
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