A module in a Verilog netlist is a collection of components similar to a SPICE subcircuit. Like paramsets, modules are declared at top level only. A module is an object inherited from BASE_SUBCKT, a COMPONENT that permits subdevices. Type resolution and elaboration is different to SPICE. Verilog has no “subtypes”: each subdevice refers to a COMPONENT by type name and has parameters and ports. The type name is resolved after read-in, and held by a stub device. Prototypes matching the type, port and parameter names of the stub are collected as candidates in precalc_first.

Once a candidate COMPONENT has undergone precalc_first, “is_valid()” indicates whether the candidate is the correct one. During expand, a cloned instance of the stub turns into a singleton subcircuit holding the valid candidate.

This singleton subcircuit is then deflated into just the candidate instance by the parent module at the end of expand.

According the the Verilog standard, only paramset, a special COMPONENT type permits overloading. In Gnucap any type name can refer to multiple prototypes.

A paramset is a COMPONENT with a named reference to another of an underlying type and a set of parameters, similar to a one-device subcircuit. The type name is resolved during precalc_first and must be unique. Port names are inherited from this prototype and available after precalc_first.

example

paramset res resistor
  parameter R;
 .r(R)
endparamset

Paramsets are declared at top level only, and ready before instances are elaborated when the containing modules are expanded.

The standard allows multiple paramset declarations with the same label (type name). In Gnucap, type resolution is implemented equally for all COMPONENTS.

During elaboration, paramset instances are flattened. An instance R1, as in

module main();
  res #(.R(r0)) R1(a, b);
endmodule

Is transformed into

resistor #(.r(r0)) R1(.p(a), .n(b));

after “paramset res” has been identified as the only valid, matching prototype. If there are multiple candidates, such as an additional

paramset res resistor
  parameter r;
 .r(r)
endparamset

the user is responsible that only one is valid. The tie braking rules from the standard are not implemented.