Verilog-AMS is a widely used standardised modelling language for physical systems, such as electronic circuits. In this project we will continue the work on a first free/libre reference implementation. The overall goals are to improve simulation in terms of speed and feature coverage.

We will implement more of the standards, specifically features related to the digital domain. New features will include the delay and signal strength modelling capabilities as well as sparse output in form of value change dumps. We will reassess and improve the performance of Verilog behavioural models and revise the mixed mode simulation algorithm. We will enhance the compatibility with Spice simulators improving the upgrade path from Spice based modelling applications. This includes the syntactical support for popular behavioural modelling devices enhancing the use of existing Spice macros within a Verilog environment. Basic scripting commands compatible with Nutmeg will be provided.

We will continue the work related to data exchange between EDA tools, such as schematic and layout editors. We will extend towards compatible device representation that works across different applications enabling the seamless interchange of complete circuit models.

The node ordering method found during work on the trace algorithm needs to be isolated and applied to matrix node before the matrix is allocated. Node orderings will enhance the speed of the LU decomposition, not just the discrete simulation.

There are gaps in the code generation related to digital signals and “always blocks”. Digital signals will be associated with nodes, and purely discrete nodes need some cleanup…

We will to implement the connect..resolveto statement to control discipline selection. These rules determine the type of the instanciated node when nets of different types are connected.

Given the types inferred in c, and the signal directions, we can finally plug in the required connectmodules.

Selective trace is working for devices in “digital” mode, and devices using “hard events”. We need to extend to soft events and populate the respective evaluation queues following analog activity in the circuit.

Similar to the matrix interface, we need a plug-in interface for node ordering algorithms. Optimal node orderings are notoriously hard to find, and normally different heuristics are considered to allow for different tradeoffs.

We use data structures to share static data across devices. We will fully implement the pruning that will free memory and will make sure only one shared object is used for each set of identical instances. This is a prerequisite for caches that will speed up evalution in some device classes.

Modelgen-verilog does not properly avoid unused derivatives. In a device with n internal states and m ports, we carry along up to n+m derivatives per floating point variable. This work will improve performance in big monolithic semiconductor compact device models wrt compilation times, memory footprint and evaluation speed.

We have implemented basic UDP in the previous round. These consist of “combinational” truth tables involving signal levels. We need to catch up on both edge sensitive UDPs as well as on sequential UDP. We will use code and/or inspiration from Icarus-Verilog as much as possible.

Verilog supports continuous and procedural assignments. Continuous assignments correspond to subdevice instances that are sensitive to the rhs of the expression, and drive the lhs. Procedural assignments correspond to state variables as used in analog models. Both concepts exist in modelgen-verilog, and will be made available for logic modelling.

IEEE1346 defines functions for random number generation following various distributions. We will implement these for analog and digital/discrete modelling.

Section 18, IEEE13634. Value Change Dump files are used to store simulator output in a standard way. We will implement the $dumpfile task.

ngSpice manual Section 5 “B” sources. We will implement the expression arguments and behaviour. This will later help converting subcircuit macros to Verilog-A code. B sources correspond to analog blocks with a single branch contribution in it. ==

Gnucap supports command plugins and function plugins. ngSpice has a ”.func” command (Section 2.10). We will implement a command that creates functions from expressions.

In Gnucap/Verilog the mapping from device instanciation to device prototype is implemented in terms of a self inflating device stub. The usual Spice simulators provide similar methods, but grouped by device class, which is sometimes unknown, sometimes irrelevant. We will implement a unified approach to device selection, instanciation and overloading.

Add scripting commands as implemented in “nutmeg”, which is a part of Spice including ngSpice and others. We have some, but it is incomplete. This Milestone will add basic support for loops and enhance measurements.

The device library in Qucs is not portable and not very useful outside of Qucs. We will replace it by ordinary Verilog files, stashing Qucs specialties in attributes. This is analogous to the recent file format upgrade. It will decouple circuit modelling from the choice of a specific tool.

We will add support for parameters and net types (disciplines) to the Qucs schematic editor. This will make accessible a rich set of features when using a Verilog-AMS simulator.

Both projects edit schematics, and schematics can be represented in Verilog, virtually without loss. We will fill some gaps, so a schematic written by one tool can be opened by the other, preserving the intended data.

Implement tests, compare/confirm simulation across tools, e.g. ngspice. Possibly port PDK to Verilog as needed for testing. Testing Spice features goes along with spice compatibility, Task 4. Implements the “MOSFET Test procedures”, the Gnucap and Verilog-AMS MOSFET testing.